1. Field of the Invention
The present invention relates to apparatus which convert a DC supply voltage into an alternating voltage; and more particularly to such apparatus, such as motor drives and power inverters, that control electricity supplied to an electric motor.
2. Description of the Related Art
Motor drives are commonly employed to control the application of electricity to a three-phase induction motor. Such motor drives include an inverter which switches DC voltage to output lines in a pulse width modulated (PWM) manner so as to control the frequency and amount of voltage applied to the motor and thus the motor speed.
One type of an inverter, known as a two-level inverter, produces pulse width modulated (PWM) waveforms which have two voltage levels, formed by a positive voltage and a negative voltage pulses, with the width of each voltage pulse being varied to create the effective voltage level being desired. A two-level inverter generates high common-mode voltage and high transient voltages at the terminals of a motor.
In another type of inverter, known as a three-level inverter, the output voltage waveform applied to the motor has three levels, formed by a positive voltage, zero volts, and a negative voltage pulses. Lower common-mode voltage and lower transient voltages can be obtained in a three-level inverter than with a two-level inverter.
A three-level inverter has a pair of capacitors connected between the two DC supply buses to divide the DC input voltage in two and produce the zero voltage level at a “neutral node” between the two capacitors. The inverter comprises a series of switches which selectively connect the three-phase output terminals to the positive voltage bus, the negative voltage bus or the neutral node in order to produce the three voltage levels. To obtain voltage and current waveforms with low harmonic content, it is desired that the voltages across the capacitors remain balanced with low ripple.
However, the voltages across the two capacitors frequently become unbalanced during operation of a three-level inverter. This imbalance results from DC components of current flowing into and out of the neutral node under transient conditions, such as when the load applied to the motor suddenly changes. As a consequence of this voltage imbalance, the voltage level of the PWM waveform produced by connecting the neutral node to an output phase terminal is not equivalent to zero volts. The voltage rating of the switches in a three-level inverter is based on one-half the DC input voltage. Any imbalance between the capacitor voltages could result in high voltage on some of the switches and could potentially damage them.
One modulation technique for a three-level inverter is known as carrier-based pulse width modulation. In this technique, there are two different modulation modes, known as the dipolar mode and the unipolar mode, as described in “A Novel Approach to the Generation and Optimization of Three-Level PWM waveforms,” PESC '88 Proceedings, pp. 1255-1262. In the dipolar mode, the inverter outputs positive voltage, zero voltage and negative voltage pulses in each PWM period, which is suitable for creating very small output voltages to operate the motor at low speed. In the unipolar mode, the inverter produces either positive voltage and zero voltage pulses or negative voltage and zero voltage pulses in a PWM period. This latter mode is more suitable for obtaining higher output voltages and thus, higher motor speeds.
Various approaches have been applied in an attempt to eliminate the capacitor voltage imbalance and thus the DC voltage offset in the PWM output waveform. In one approach, described in U.S. Pat. No. 4,953,069, the voltage balancing method works only for the dipolar mode. Another approach, described in U.S. Pat. No. 5,361,196, deals with the voltage balancing problem in both the dipolar mode and the unipolar mode. However, this technique was found to have several short comings. It was observed that the phase-to-neutral voltage waveform had transitions occurring directly from the positive voltage level to the negative voltage level and visa-versa without the occurrence of an intermediate zero voltage level. These direct transitions are undesirable, as they lead to higher common-mode voltage and step heights of the DC supply bus voltage in the motor line-to-line voltage, resulting in higher transient voltages at the motor terminals, similar to a two-level inverter.
Therefore, it is desirable to provide an improved technique that addresses the capacitor imbalance problem.